1. Field of the Invention
The present invention relates to a semiconductor device including Darlington connections, and, more particularly, to an improvement for enhancing performance of the transistors in the Darlington connections included in the semiconductor device.
2. Description of the Prior Art
In general, a current amplification factor h.sub.FE is important for performance of a transistor device. In order to increase the current amplification factor, a Darlington connection has been widely used. In this case, there are two manners, one being that a plurality of devices are used for Darlington connection and the other being that the Darlington connection is structured by a single device. Recently, the latter approach has been widely used since it is advantageous for miniaturization.
FIG. 1 is a Darlington circuit structured by two devices. The Darlington connection shown in FIG. 1 includes two transistors T.sub.r1 and T.sub.r2 having, respectively, collectors C1 and C2, emitters E1 and E2, and bases B1 and B2. I.sub.C denotes a collector current, I.sub.E denotes an emitter current and I.sub.B denotes a base current. Assuming that the current amplification factors of the first stage transistor T.sub.r1 and the second stage transistor T.sub.r2 are h.sub.FE1 and h.sub.FE2, respectively, whole current amplification factor h.sub.FE equals to h.sub.FE1.h.sub.FE2. Since the factors h.sub.FE1 and h.sub.FE2 both are sufficiently larger than 1, the whole current amplification factor h.sub.FE becomes considerably larger as compared with that in a single transistor. As a result, a current flowing into the second stage transistor T.sub.r2 becomes larger than a current flowing into the first stage transistor T.sub.r1 and hence, if and when both transistors are structured by using the same material, the size, that is, a chip area, of the second stage transistor T.sub.r2 must be made larger than that of the first stage transistor T.sub.r1.
FIG. 2 is a Darlington connection structured by using a single device, wherein the same portions as in FIG. 1 are shown by the same reference numerals except for a prime ('). In this structure, since the resistance in an area structuring a base B'.sub.2 of the second stage transistor T'.sub.r2 becomes larger because of an increased size of the second stage transistor T'.sub.r2, that is, an increased area on a semiconductor chip as described in the foregoing, a resistor R'.sub.1 is inserted between the emitter E'.sub.1 of the first stage transistor T'.sub.r1 and a base B'.sub.2 of the second stage transistor T'.sub.r2. In case where the value of the resistor R'.sub.1 is large, the current amplification factor h.sub.FE is decreased. However, with the Darlington connection of two stages as shown in FIG. 2, the effect of reduction of the current amplification factor is relatively small, while a meritorious effect for miniaturization of the apparatus is greater.
FIG. 3 shows a circuit diagram of Darlington connections comprised of three transistors in a single device, which is referred to as a three-stage Darlington device hereinafter. In FIG. 3, C'.sub.1, E'.sub.1, B'.sub.1 denote, respectively, a collector, an emitter, and a base in the first stage; C'.sub.2, E'.sub.2, B'.sub.2 denote, respectively, a collector, an emitter and a base of the second stage; and C'.sub.3, E'.sub.3 and B'.sub.3 denote, respectively, a collector, an emitter and a base in the third stage. A resistor R'.sub.1 connected between the emitter E'.sub.1 of the first stage transistor and the base B'.sub.2 of the second stage transistor is a resistor of the three-stage Darlington device which has effect on the current amplification factor. Since a current flowing into the second stage transistor is larger than that in the first stage transistor and a current flowing into the third stage transistor is larger than that in the second stage transistor, areas occupied on the chip become larger sequentially, which is diagrammatically represented in FIG. 3. The basic purpose of the three-stage Darlington device is to make a current amplification factor larger and to structure the device in a single device for miniaturization of a module. In addition, in order to withstand an external voltage applied to the device, that is, in order to increase its breakdown voltage, it is necessary to use materials with high specific resistance. Accordingly, there is a relation of R'.sub.2 &gt;&gt;R'.sub.1 in their resistance between the resistors R'.sub.1 and R'.sub.2 and thus the resistor R'.sub.2 has greater effect on a current amplification factor than the case in FIG. 2, which causes many problems in practice.
More particularly, a specific structure of a conventional three-stage Darlington device will be described in the following. FIG. 4 is a plan view showing a specific structure of a conventional three-stage Darlington device, FIGS. 5 and 6 are cross-sectional views taken along the lines V--V and V1--V1, respectively, in FIG. 4, and FIG. 7 is a perspective view of the three-stage Darlington device.
Referring to these figures, a common collector layer 2 of n.sup.- type is deposited on a n.sup.+ type of semiconductor substrate 1. Then, a plurality of, (in this example three), base regions 3, 4 and 5 of P type are formed in the common collector layer 2 by diffusion process. The three base regions 3, 4 and 5 constitute the base B'.sub.1 of the first stage transistor, the base B'.sub.2 of the second stage transistor and the base B'.sub.3 of the third stage transistor, respectively. An n type region 6 constituting the emitter, E'.sub.1 of the first stage transistor is formed in the base B'.sub.1 region 3 and an n type region 7 constituting the emitter E'.sub.2 of the second stage transistor is formed in the base B'.sub.2 region 4. In addition, a plurality of, (in this example, 6), n type regions 8a, 8b-8f constituting the emitter E'.sub.3 by connecting the regions 8a, 8b,-8f in parallel are formed in the base B'.sub.3 region 5. Then, a metallization layer 9 is formed such that the three transistors are, in turn, connected in a Darlington configuration. To this end, an insulating layer 10 (FIGS. 5 and 6) is provided for insulating different portions of the metallization layer 9 from each other so that necessary Darlington connection is achieved. Bonding regions 11, 11 are formed on the metallization layer 9 on the emitter region 8a, 8b-8f for connecting the emitter E'.sub.3 to an external circuit.
As shown in FIGS. 4 to 6, although a current entering from the emitter E'.sub.2 of the second stage transistor into the base B'.sub.3 of the third stage transistor flows separately into the metallization layer 9 of the surface and into the P type base diffussion layer 5, the resistance of the P type diffusion layer 5 has much effect on a current amplification factor since the metallization layer 9 is thin, and thus the current amplification factor decreases.